Re: [rtl] CPLD's - JTAG & JAM

[smithk@biotronik.com (Kirk Smith)]

> From:          John Storrs <lme@storrs.demon.co.uk>
> Reply-to:      lme@storrs.demon.co.uk
> To:            rtl@rtlinux.cs.nmt.edu
> Subject:       Re: [rtl] CPLD's - JTAG & JAM
> Date:          Sun, 14 Mar 1999 10:18:59 +0000

> 
> >On Fri, 12 Mar 1999, Victor wrote:
> 
> On further thought, I don't know of any ISP devices you can treat like RAM.
> Don't they all have limited reprogrammability? In the case of Lattice, they
> quote 10k times. This precludes real dynamic programming. You could kill the
> device in about 10k seconds.
>

FPGA, or atleast Xilinx's Spartan series FPGA's use a RAM sturcture to store 
Gate programs, (i.e. loosing power looses gate functionality).  So if you have 
an embedded processor available to load the FPGA on boot up (or a serial 
EEPROM) the FPGA has unlimited writes. 
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